Digital circuitry has played an important role in the growth of electronic industries. As the cost of equipment for performing digital operations is reduced, digital circuits replace more and more analog circuits and find new applications previously not contemplated.
Developments enabling the fabrication of large scale integrated logic circuit arrays have reduced the potential cost of digital equipment. Thousands of devices can be created on a semiconductor substrate which previously was employed for one device. As the size of semiconductor devices is reduced and their packing density is thereby increased, the electrical and thermal parameters which affect the design of such circuitry are altered. For example, as the size of a MOSFET is reduced, the minimum obtainable source-to-drain impedance is increased. As components are placed more closely together, stray capacity is reduced and average allowable power dissipation for each device is reduced. Further, because of the compact arrangement, bringing excess leads to the circuitry increases the complexity thereof.
New circuit configurations have been developed to take these new parameters into account, providing circuits more suitable for large scale integration. A straightforward appraoch to implementing logical functions in MOSFET integrated circuits involves a logic network including a plurality of FET devices to provide either an open or short circuit depending upon the logical state thereof in series with an FET load device. The series circuit is connected between two reference voltage levels. A gating FET device connects the junction of the logic network and the load FET to drive another logic stage or a load device, either of which may be a capacitor. The gating FET is periodically enabled to transfer the logical level at the junction of the load FET and the logic network to the capacitor.
This configuration suffers from several disadvantages. The soure-to-drain impedance of the load FET must bear a known relationship to the impedance of the logic network in its ON and OFF states. This places a constraint on the parameters of the FET devices used therein lowering the yield, since each device must have parameters within a limited range. Further, when the logic network is in its ON state, current is continuously flowing in the load device and the logic network, therefore dissipating power. Also, all devices cannot be minimum size devices due to the impedance relationships and therefore layout efficiency is sacrificed. Finally, two power supply leads must be brought to the circuit decreasing layout efficiency.
U.S. Pat. No. 3,365,707 entitled "LSI Array and Standard Cells," which issued to T. R. Mayhew on Jan. 23, 1968, discloses a dynamically clocked logic circuit in which a logic circuit as above described is modified by gating the load FET as well as the gating FET. In this arrangement current flows only during the gating process. Therefore, the power dissipation in the circit is reduced. Standby current still flows, however, during gating and the other disadvantages still remain.
Another type of logic circuit employing large scale integrated circuits includes a gated load transistor in series with a second gating transistor also in series with a logic network. The series chain is connected between two voltage levels. The gated load transistor is pulsed to charge an output capacitor. After the output capacitor is charged, the load transistor is turned OFF and the second gating transistor is pulsed to discharge the capacitor if the logic network provides a short. In this way, an open circuit logic network leaves th voltage on the capacitor while the shorted logic circuit discharges it. In this circuit, no standing current is required, minimizing the power dissipated in performing logic functions. The impedance values of the various FET devices may vary over a wide range without affecting circuit operation. This arrangement, however, still requires two FET's in addition to the logic network. Power supply leads must still be brought to the circuit. This circuit also requires two clocking pulses as opposed to one for each stage of logic.